Title: | module placement with boundary constraints using o-tree representation |
Author: | Liu R
; Hong XL
; Dong SQ
; Cai YC
; Gu J
; Cheng CK
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Conference Name: | IEEE International Symposium on Circuits and Systems
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Conference Date: | MAY 26-29,
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Issued Date: | 2002
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Conference Place: | PHOENIX, AZ
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Keyword: | I/O pad connection
; O-tree representation
; VLSI physical design
; boundary constraints
; chip boundary placement
; layout generation
; linear computation effort
; module placement
; polynomial methods
; simulated annealing based algorithm
; circuit optimisation
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Publisher: | 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS
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Publish Place: | 345 E 47TH ST, NEW YORK, NY 10017 USA
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Indexed Type: | istp
; ieee
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ISBN: | 0-7803-7448-7
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Department: | Chinese Acad Sci, Inst Software, Beijing, Peoples R China.
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Sponsorship: | IEEE, IEEE Circuits & Syst Soc
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English Abstract: | The O-tree representation needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper bound of possible configurations. This paper addresses the problem of handling boundary constraints in the context of O- |
Language: | 英语
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Content Type: | 会议论文
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URI: | http://ir.iscas.ac.cn/handle/311060/13390
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Appears in Collections: | 软件所图书馆_会议论文
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01011492.pdf(320KB) | -- | -- | 限制开放 | -- | 联系获取全文 |
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Recommended Citation: |
Liu R,Hong XL,Dong SQ,et al. module placement with boundary constraints using o-tree representation[C]. 见:IEEE International Symposium on Circuits and Systems. PHOENIX, AZ. MAY 26-29,.
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