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题名:
module placement with boundary constraints using o-tree representation
作者: Liu R ; Hong XL ; Dong SQ ; Cai YC ; Gu J ; Cheng CK
会议名称: IEEE International Symposium on Circuits and Systems
会议日期: MAY 26-29,
出版日期: 2002
会议地点: PHOENIX, AZ
关键词: I/O pad connection ; O-tree representation ; VLSI physical design ; boundary constraints ; chip boundary placement ; layout generation ; linear computation effort ; module placement ; polynomial methods ; simulated annealing based algorithm ; circuit optimisation
出版者: 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS
出版地: 345 E 47TH ST, NEW YORK, NY 10017 USA
收录类别: istp ; ieee
ISBN: 0-7803-7448-7
部门归属: Chinese Acad Sci, Inst Software, Beijing, Peoples R China.
主办者: IEEE, IEEE Circuits & Syst Soc
英文摘要: The O-tree representation needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper bound of possible configurations. This paper addresses the problem of handling boundary constraints in the context of O-
语种: 英语
内容类型: 会议论文
URI标识: http://ir.iscas.ac.cn/handle/311060/13390
Appears in Collections:软件所图书馆_会议论文

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Recommended Citation:
Liu R,Hong XL,Dong SQ,et al. module placement with boundary constraints using o-tree representation[C]. 见:IEEE International Symposium on Circuits and Systems. PHOENIX, AZ. MAY 26-29,.
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