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Title:
low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan
Author: Zhang Zhen-Dong ; Wu Bin ; Zhou Yu-Mei ; Zhang Xin
Keyword: CMOS integrated circuits ; Harmonic analysis ; Standards
Source: VLSI Design
Issued Date: 2012
Volume: 2012, Pages:-
Indexed Type: EI
Department: (1) ASIC and System Department Institute of Microelectronics of Chinese Academy of Sciences Beijing 100029 China; (2) DSP Software Department Datang Mobile Communications Equipment Co. Ltd. Beijing 100083 China
Abstract: A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm2, and the synthesized maximal working frequency is 400MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility. Copyright © 2012 Zhen-dong Zhang et al.
English Abstract: A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm2, and the synthesized maximal working frequency is 400MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility. Copyright © 2012 Zhen-dong Zhang et al.
Language: 英语
Content Type: 期刊论文
URI: http://ir.iscas.ac.cn/handle/311060/15413
Appears in Collections:软件所图书馆_期刊论文

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Recommended Citation:
Zhang Zhen-Dong,Wu Bin,Zhou Yu-Mei,et al. low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan[J]. VLSI Design,2012-01-01,2012:-.
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