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Title:
algorithm for communication synchronization on reconfigurable processor arrays with faults
Author: Wu Jigang ; Jiang Guiyuan ; Zhang Yuanrui ; Zhu Yuanbo
Source: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Conference Name: 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Conference Date: May 21, 2012 - May 25, 2012
Issued Date: 2012
Conference Place: Shanghai, China
Keyword: Algorithms ; Communication ; Distributed parameter networks ; Fault tolerance
Indexed Type: EI
ISBN: 9780769546766
Department: (1) School of Computer Science and Software Engineering Tianjin Polytechnic University 300387 Tianjin China; (2) State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences 100190 Beijing China; (3) School of Computer Science and Technology Tianjin University 300072 Tianjin China
Sponsorship: IEEE Computer Society Technical Committee on Parallel Processing
Abstract: Efficient fault tolerant techniques for reconfigurable multiprocessor array have been extensively studied to construct maximum target array from host array with faulty processors. Existing work focused on the reconfiguration algorithm without considering the communication synchronization of the target array. This paper proposes an algorithm to rearrange the long interconnects of the target array, in order to improve the communication performance in synchronization. In addition, divide and conquer strategy is utilized for deleting logical rows to form a high performance target array with given size. Experimental results show that the proposed algorithm achieves considerable improvement on communication performance in synchronization for the case of small fault rate which is often occurred in real applications. © 2012 IEEE.
English Abstract: Efficient fault tolerant techniques for reconfigurable multiprocessor array have been extensively studied to construct maximum target array from host array with faulty processors. Existing work focused on the reconfiguration algorithm without considering the communication synchronization of the target array. This paper proposes an algorithm to rearrange the long interconnects of the target array, in order to improve the communication performance in synchronization. In addition, divide and conquer strategy is utilized for deleting logical rows to form a high performance target array with given size. Experimental results show that the proposed algorithm achieves considerable improvement on communication performance in synchronization for the case of small fault rate which is often occurred in real applications. © 2012 IEEE.
Language: 英语
Content Type: 会议论文
URI: http://ir.iscas.ac.cn/handle/311060/15769
Appears in Collections:软件所图书馆_会议论文

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Recommended Citation:
Wu Jigang,Jiang Guiyuan,Zhang Yuanrui,et al. algorithm for communication synchronization on reconfigurable processor arrays with faults[C]. 见:2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012. Shanghai, China. May 21, 2012 - May 25, 2012.
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