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Title:
efficient reconfiguration algorithm for three-dimensional vlsi arrays
Author: Jiang Guiyuan ; Jigang Wu ; Sun Jizhou
Source: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Conference Name: 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Conference Date: May 21, 2012 - May 25, 2012
Issued Date: 2012
Conference Place: Shanghai, China
Keyword: Algorithms ; Distributed parameter networks ; Fault tolerance ; Heuristic algorithms ; Parallel architectures ; Reconfigurable architectures ; Three dimensional computer graphics
Indexed Type: EI
ISBN: 9780769546766
Department: (1) School of Computer Science and Technology Tianjin University 300072 Tianjin China; (2) School of Computer Science and Software Engineering Tianjin Polytechnic University 300387 Tianjin China; (3) State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences 100190 Beijing China
Sponsorship: IEEE Computer Society Technical Committee on Parallel Processing
Abstract: Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to reconfigure a 3D host array with faults resulting in a target sub-array without faults. Moreover, a heuristic algorithm based on plane rerouting is proposed to construct a target sub-array on the selected rows and columns. It is also proved that the reconfiguration problem considered in this paper on the selected rows and columns(MPSRC) can be optimally solvable in linear time. Empirical study shows that the proposed algorithm produces target arrays with good harvest for the case of the fault rate no more than 5%, that is often occurred in real applications. © 2012 IEEE.
English Abstract: Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to reconfigure a 3D host array with faults resulting in a target sub-array without faults. Moreover, a heuristic algorithm based on plane rerouting is proposed to construct a target sub-array on the selected rows and columns. It is also proved that the reconfiguration problem considered in this paper on the selected rows and columns(MPSRC) can be optimally solvable in linear time. Empirical study shows that the proposed algorithm produces target arrays with good harvest for the case of the fault rate no more than 5%, that is often occurred in real applications. © 2012 IEEE.
Language: 英语
Content Type: 会议论文
URI: http://ir.iscas.ac.cn/handle/311060/15781
Appears in Collections:软件所图书馆_会议论文

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Recommended Citation:
Jiang Guiyuan,Jigang Wu,Sun Jizhou. efficient reconfiguration algorithm for three-dimensional vlsi arrays[C]. 见:2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012. Shanghai, China. May 21, 2012 - May 25, 2012.
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