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Title:
virtual circuit model for low power scan testing in linear decompressor-based compression environment
Author: Chen Zhen ; Li Jia ; Xiang Dong ; Huang Yu
Source: Proceedings of the Asian Test Symposium
Conference Name: 20th Asian Test Symposium, ATS 2011
Conference Date: November 20, 2011 - November 23, 2011
Issued Date: 2011
Conference Place: New Delhi, India
Keyword: Circuit theory ; Filling ; Low power electronics
Indexed Type: EI
ISSN: 1081-7735
ISBN: 9780769545837
Department: (1) Tsinghua National Laboratory for Information Science and Technology Tsinghua University Beijing 100084 China; (2) Dept. of Comp. Sci. and Techn. Tsinghua University Beijing 100084 China; (3) Integrated Circuit Advaced Process Center Institute of Microelectronics Chinese Academy of Sciences 100029 Beijing China; (4) School of Software Tsinghua University Beijing 100084 China; (5) Mentor Graphics Corporation Wilsonville OR 97070 United States
Sponsorship: Indraprastha Institute of Information Technology (IIIT); VLSI Society of India
Abstract: Large test data volume and high test power consumption are two major concerns for the industry when testing large integrated circuits. Linear decompress or-based compression (LDC) is efficient in reducing test data volume, while X-filling during ATPG can efficiently reduce test power with low overhead. However, traditional X-filling methods cannot be reused in the LDC environment. In this paper, we propose a virtual circuit model to make the linear de-compressor transparent to the external testing. As a result, existing X-filling methods can be reused to reduce test power. Experimental results on benchmark circuits demonstrate the effciency of the proposed approach. © 2011 IEEE.
English Abstract: Large test data volume and high test power consumption are two major concerns for the industry when testing large integrated circuits. Linear decompress or-based compression (LDC) is efficient in reducing test data volume, while X-filling during ATPG can efficiently reduce test power with low overhead. However, traditional X-filling methods cannot be reused in the LDC environment. In this paper, we propose a virtual circuit model to make the linear de-compressor transparent to the external testing. As a result, existing X-filling methods can be reused to reduce test power. Experimental results on benchmark circuits demonstrate the effciency of the proposed approach. © 2011 IEEE.
Language: 英语
Content Type: 会议论文
URI: http://ir.iscas.ac.cn/handle/311060/16314
Appears in Collections:软件所图书馆_会议论文

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Recommended Citation:
Chen Zhen,Li Jia,Xiang Dong,et al. virtual circuit model for low power scan testing in linear decompressor-based compression environment[C]. 见:20th Asian Test Symposium, ATS 2011. New Delhi, India. November 20, 2011 - November 23, 2011.
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