Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT

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	Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
	Victor Khomenko; Maciej Koutny; Alex Yakovlev
	2005
Source	Fundamenta Informaticae
Volume	70 Issue:1 Pages:49 - 73
Indexed Type	其他
Cooperation Status	其它
Language	中文
Content Type	期刊论文
URI	http://ir.iscas.ac.cn/handle/311060/1220
Collection	中国科学院软件研究所
Recommended Citation GB/T 7714	Victor Khomenko,Maciej Koutny,Alex Yakovlev. Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT[J]. Fundamenta Informaticae,2005,70(1):49 - 73.
APA	Victor Khomenko,Maciej Koutny,&Alex Yakovlev.(2005).Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT.Fundamenta Informaticae,70(1),49 - 73.
MLA	Victor Khomenko,et al."Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT".Fundamenta Informaticae 70.1(2005):49 - 73.

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