Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT

ISCAS OpenIR

	Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
	Victor Khomenko; Maciej Koutny; Alex Yakovlev
	2005
发表期刊	Fundamenta Informaticae
卷号	70 期号:1 页码:49 - 73
收录类别	其他
合作性质	其它
语种	中文
内容类型	期刊论文
URI标识	http://ir.iscas.ac.cn/handle/311060/1220
专题	中国科学院软件研究所
推荐引用方式 GB/T 7714	Victor Khomenko,Maciej Koutny,Alex Yakovlev. Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT[J]. Fundamenta Informaticae,2005,70(1):49 - 73.
APA	Victor Khomenko,Maciej Koutny,&Alex Yakovlev.(2005).Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT.Fundamenta Informaticae,70(1),49 - 73.
MLA	Victor Khomenko,et al."Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT".Fundamenta Informaticae 70.1(2005):49 - 73.