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| module placement with boundary constraints using o-tree representation | |
| Liu R; Hong XL; Dong SQ; Cai YC; Gu J; Cheng CK | |
| 2002 | |
| Conference Name | IEEE International Symposium on Circuits and Systems |
| Pages | 871-874 |
| Conference Date | MAY 26-29, |
| Conference Place | PHOENIX, AZ |
| Indexed Type | istp ; ieee |
| Publish Place | 345 E 47TH ST, NEW YORK, NY 10017 USA |
| Publisher | 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS |
| ISBN | 0-7803-7448-7 |
| Department | Chinese Acad Sci, Inst Software, Beijing, Peoples R China. |
| English Abstract | The O-tree representation needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper bound of possible configurations. This paper addresses the problem of handling boundary constraints in the context of O- |
| Keyword | I/o Pad Connection O-tree Representation Vlsi Physical Design Boundary Constraints Chip Boundary Placement Layout Generation Linear Computation Effort Module Placement Polynomial Methods Simulated Annealing Based Algorithm Circuit Optimisation |
| Sponsorship | IEEE, IEEE Circuits & Syst Soc |
| Language | 英语 |
| Content Type | 会议论文 |
| URI | http://ir.iscas.ac.cn/handle/311060/13390 |
| Collection | 中国科学院软件研究所 |
| Recommended Citation GB/T 7714 | Liu R,Hong XL,Dong SQ,et al. module placement with boundary constraints using o-tree representation[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS,2002:871-874. |
| Files in This Item: | ||||||
| File Name/Size | DocType | Version | Access | License | ||
| 01011492.pdf（320KB） | 开放获取 | -- | Application Full Text | |||
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