Institutional Repository
| hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices | |
| Liu Peng; Wu Jigang; Wang Yongji | |
| 2012 | |
| 发表期刊 | Mathematical and Computer Modelling
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| ISSN | 0895-7177 |
| 页码 | - |
| 摘要 | Hardware/software (HW/SW) partitioning and scheduling are essential to embedded systems. In this paper, a hybrid algorithm derived from Tabu Search (TS) and Simulated Annealing (SA) is proposed for solving the HW/SW partitioning problem. The annealing procedure of SA is employed to accelerate the updating of Tabu tables for task scheduling, and the virtual hardware resource is also set to implement the customized TS. The Earliest-Deadline-First (EDF) strategy is introduced to describe the reconfiguration of FPGA. Moreover, an algorithm combining the Breadth-First-Search (BFS) with Depth-First-Search (DFS) is proposed for HW/SW task scheduling to fit the features of reconfigurable systems. Experimental results show that the improvement over the latest efficient combinatorial algorithm is up to 50%. The proposed virtual hardware expanding technique makes the performance increase up to 97.51% on random graphs. The improvement on task scheduling is by 50% in comparison to popular algorithms cited in this paper. © 2012 Elsevier Ltd. All rights reserved.; Hardware/software (HW/SW) partitioning and scheduling are essential to embedded systems. In this paper, a hybrid algorithm derived from Tabu Search (TS) and Simulated Annealing (SA) is proposed for solving the HW/SW partitioning problem. The annealing procedure of SA is employed to accelerate the updating of Tabu tables for task scheduling, and the virtual hardware resource is also set to implement the customized TS. The Earliest-Deadline-First (EDF) strategy is introduced to describe the reconfiguration of FPGA. Moreover, an algorithm combining the Breadth-First-Search (BFS) with Depth-First-Search (DFS) is proposed for HW/SW task scheduling to fit the features of reconfigurable systems. Experimental results show that the improvement over the latest efficient combinatorial algorithm is up to 50%. The proposed virtual hardware expanding technique makes the performance increase up to 97.51% on random graphs. The improvement on task scheduling is by 50% in comparison to popular algorithms cited in this paper. © 2012 Elsevier Ltd. All rights reserved. |
| 收录类别 | EI |
| 关键词 | Computer Hardware Field Programmable Gate Arrays (Fpga) Hardware Multitasking Response Time (Computer Systems) Scheduling Scheduling Algorithms Simulated Annealing Tabu Search |
| 部门归属 | (1) School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin 300387 China; (2) State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijing 100190 China |
| 语种 | 英语 |
| WOS记录号 | WOS:000320601000042 |
| 引用统计 | |
| 内容类型 | 期刊论文 |
| URI标识 | http://ir.iscas.ac.cn/handle/311060/15156 |
| 专题 | 中国科学院软件研究所 |
| 推荐引用方式 GB/T 7714 | Liu Peng,Wu Jigang,Wang Yongji. hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices[J]. Mathematical and Computer Modelling,2012:-. |
| APA | Liu Peng,Wu Jigang,&Wang Yongji.(2012).hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices.Mathematical and Computer Modelling,-. |
| MLA | Liu Peng,et al."hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices".Mathematical and Computer Modelling (2012):-. |
| 条目包含的文件 | 条目无相关文件。 | |||||
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