low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan

ISCAS OpenIR

	low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan
	Zhang Zhen-Dong; Wu Bin; Zhou Yu-Mei; Zhang Xin
	2012
发表期刊	VLSI Design
ISSN	1065-514X
卷号	2012 页码:-
摘要	A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm², and the synthesized maximal working frequency is 400MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility. Copyright © 2012 Zhen-dong Zhang et al.; A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm², and the synthesized maximal working frequency is 400MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility. Copyright © 2012 Zhen-dong Zhang et al.
收录类别	EI
关键词	Cmos Integrated Circuits Harmonic Analysis Standards
部门归属	(1) ASIC and System Department Institute of Microelectronics of Chinese Academy of Sciences Beijing 100029 China; (2) DSP Software Department Datang Mobile Communications Equipment Co. Ltd. Beijing 100083 China
语种	英语
内容类型	期刊论文
URI标识	http://ir.iscas.ac.cn/handle/311060/15413
专题	中国科学院软件研究所
推荐引用方式 GB/T 7714	Zhang Zhen-Dong,Wu Bin,Zhou Yu-Mei,et al. low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan[J]. VLSI Design,2012,2012:-.
APA	Zhang Zhen-Dong,Wu Bin,Zhou Yu-Mei,&Zhang Xin.(2012).low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan.VLSI Design,2012,-.
MLA	Zhang Zhen-Dong,et al."low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan".VLSI Design 2012(2012):-.