algorithm for communication synchronization on reconfigurable processor arrays with faults

ISCAS OpenIR

	algorithm for communication synchronization on reconfigurable processor arrays with faults
	Wu Jigang; Jiang Guiyuan; Zhang Yuanrui; Zhu Yuanbo
	2012
会议名称	2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
会议录名称	Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
页码	266-270
会议日期	May 21, 2012 - May 25, 2012
会议地点	Shanghai, China
收录类别	EI
ISBN	9780769546766
部门归属	(1) School of Computer Science and Software Engineering Tianjin Polytechnic University 300387 Tianjin China; (2) State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences 100190 Beijing China; (3) School of Computer Science and Technology Tianjin University 300072 Tianjin China
摘要	Efficient fault tolerant techniques for reconfigurable multiprocessor array have been extensively studied to construct maximum target array from host array with faulty processors. Existing work focused on the reconfiguration algorithm without considering the communication synchronization of the target array. This paper proposes an algorithm to rearrange the long interconnects of the target array, in order to improve the communication performance in synchronization. In addition, divide and conquer strategy is utilized for deleting logical rows to form a high performance target array with given size. Experimental results show that the proposed algorithm achieves considerable improvement on communication performance in synchronization for the case of small fault rate which is often occurred in real applications. © 2012 IEEE.; Efficient fault tolerant techniques for reconfigurable multiprocessor array have been extensively studied to construct maximum target array from host array with faulty processors. Existing work focused on the reconfiguration algorithm without considering the communication synchronization of the target array. This paper proposes an algorithm to rearrange the long interconnects of the target array, in order to improve the communication performance in synchronization. In addition, divide and conquer strategy is utilized for deleting logical rows to form a high performance target array with given size. Experimental results show that the proposed algorithm achieves considerable improvement on communication performance in synchronization for the case of small fault rate which is often occurred in real applications. © 2012 IEEE.
关键词	Algorithms Communication Distributed Parameter Networks Fault Tolerance
主办者	IEEE Computer Society Technical Committee on Parallel Processing
语种	英语
内容类型	会议论文
URI标识	http://ir.iscas.ac.cn/handle/311060/15769
专题	中国科学院软件研究所
推荐引用方式 GB/T 7714	Wu Jigang,Jiang Guiyuan,Zhang Yuanrui,et al. algorithm for communication synchronization on reconfigurable processor arrays with faults[C],2012:266-270.