efficient reconfiguration algorithm for three-dimensional vlsi arrays

ISCAS OpenIR

	efficient reconfiguration algorithm for three-dimensional vlsi arrays
	Jiang Guiyuan; Jigang Wu; Sun Jizhou
	2012
会议名称	2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
会议录名称	Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
页码	261-265
会议日期	May 21, 2012 - May 25, 2012
会议地点	Shanghai, China
收录类别	EI
ISBN	9780769546766
部门归属	(1) School of Computer Science and Technology Tianjin University 300072 Tianjin China; (2) School of Computer Science and Software Engineering Tianjin Polytechnic University 300387 Tianjin China; (3) State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences 100190 Beijing China
摘要	Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to reconfigure a 3D host array with faults resulting in a target sub-array without faults. Moreover, a heuristic algorithm based on plane rerouting is proposed to construct a target sub-array on the selected rows and columns. It is also proved that the reconfiguration problem considered in this paper on the selected rows and columns(MPSRC) can be optimally solvable in linear time. Empirical study shows that the proposed algorithm produces target arrays with good harvest for the case of the fault rate no more than 5%, that is often occurred in real applications. © 2012 IEEE.; Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to reconfigure a 3D host array with faults resulting in a target sub-array without faults. Moreover, a heuristic algorithm based on plane rerouting is proposed to construct a target sub-array on the selected rows and columns. It is also proved that the reconfiguration problem considered in this paper on the selected rows and columns(MPSRC) can be optimally solvable in linear time. Empirical study shows that the proposed algorithm produces target arrays with good harvest for the case of the fault rate no more than 5%, that is often occurred in real applications. © 2012 IEEE.
关键词	Algorithms Distributed Parameter Networks Fault Tolerance Heuristic Algorithms Parallel Architectures Reconfigurable Architectures Three Dimensional Computer Graphics
主办者	IEEE Computer Society Technical Committee on Parallel Processing
语种	英语
内容类型	会议论文
URI标识	http://ir.iscas.ac.cn/handle/311060/15781
专题	中国科学院软件研究所
推荐引用方式 GB/T 7714	Jiang Guiyuan,Jigang Wu,Sun Jizhou. efficient reconfiguration algorithm for three-dimensional vlsi arrays[C],2012:261-265.