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| a low power adaptive clock and data recovery circuit for wireless implantable systems | |
| Yu Hang; Li Yan; Jiang Lai; Ji Zhen; Yan Ping-Kun; Wang Fei | |
| 2011 | |
| Source | Shenzhen Daxue Xuebao (Ligong Ban)/Journal of Shenzhen University Science and Engineering
 |
| ISSN | 1000-2618 |
| Volume | 28Issue:2Pages:143-146 |
| English Abstract | An extremely low power clock and data recovery circuit was designed for pulse position modulated input. Synchronized clock and data were recovered through converting the timing distance between pulses into voltage domain. The reference voltage required for data recovery was adaptively generated to extend the range of the input data rate. The design was validated using 0.25 μm CMOS technology. With 45.5 kbits/s input data, the entire circuit only consumes less than 13 μW of power.; An extremely low power clock and data recovery circuit was designed for pulse position modulated input. Synchronized clock and data were recovered through converting the timing distance between pulses into voltage domain. The reference voltage required for data recovery was adaptively generated to extend the range of the input data rate. The design was validated using 0.25 μm CMOS technology. With 45.5 kbits/s input data, the entire circuit only consumes less than 13 μW of power. |
| Indexed Type | EI |
| Keyword | Charge Pump Circuits Clocks Cmos Integrated Circuits Design Electric Power Supplies To Apparatus Input Output Programs Integrated Circuits Jitter Metallic Compounds Mos Devices Optical Pumping Packet Switching Pulse Modulation Pulse Position Modulation Pumps Transistors |
| Department | (1) Shenzhen City Key Laboratory of Embedded System Design College of Computer Science and Software Engineering Shenzhen University Shenzhen 518060 China; (2) State Key Laboratory of Transient Optics and Photonics Xi'an Institute of Optics and Precision Mechanics Chinese Academy of Sciences Xi'an 710119 China; (3) IBM Almaden Research Center San Jose 95120 United States |
| Language | 英语 |
| Content Type | 期刊论文 |
| URI | http://ir.iscas.ac.cn/handle/311060/16175 |
| Collection | 中国科学院软件研究所 |
| Recommended Citation GB/T 7714 | Yu Hang,Li Yan,Jiang Lai,et al. a low power adaptive clock and data recovery circuit for wireless implantable systems[J]. Shenzhen Daxue Xuebao (Ligong Ban)/Journal of Shenzhen University Science and Engineering,2011,28(2):143-146. |
| APA | Yu Hang,Li Yan,Jiang Lai,Ji Zhen,Yan Ping-Kun,&Wang Fei.(2011).a low power adaptive clock and data recovery circuit for wireless implantable systems.Shenzhen Daxue Xuebao (Ligong Ban)/Journal of Shenzhen University Science and Engineering,28(2),143-146. |
| MLA | Yu Hang,et al."a low power adaptive clock and data recovery circuit for wireless implantable systems".Shenzhen Daxue Xuebao (Ligong Ban)/Journal of Shenzhen University Science and Engineering 28.2(2011):143-146. |
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