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| 模拟集成电路版图设计自动化的研究 | |
| Alternative Title | A study on analog integrated circuit layout automation |
| 刘锐 | |
| Major | 计算机应用技术 |
| 2002 | |
| Degree Grantor | 中国科学院软件研究所，清华大学计算机系 |
| Degree Level | 博士 |
| Place of Degree Grantor | 中国科学院软件研究所，清华大学计算机系 |
| Keyword | 模拟集成电路 电路版图设计 计算机辅助设计 电子设计自动化 优化设计 |
| English Abstract | 该文设计了模拟集成电路版图设计自动化工具的流程.整个流程分为输入、Stack生成、布局、布线和输出五部分.对于Stack生成阶段,提出了对称欧拉图、对称欧拉路径的概念,及其构造算法,在此基础上提出了构造二维Stack的算法,生成的二维Stack同时关于X轴和Y轴对称,并且具有公共质心结构,使得工艺、温度等因素造成的失配达到最小.在布局阶段,提出了模块之间的合并算法,进一步挖掘了几何区域共享的可能性,从而提高了面积利用率,减少了寄主.该算法本质上是独立的,可以与任何拓扑表示相结合.还提出了,在布局阶段解决基于O-tree表示的边界约束问题的算法.边界约束是为了解决某些模块因为需要输入输出,必须放置在芯片边界的问题.此外,为了解决某些模块需要沿一条预定总线放置的问题,提出了基于序列对表示的预定坐标线对准算法. |
| Abstract | Driven by the increasing need of incorporation both analog and digital circuits on the same silicon chip, design automation for analog integrated circuits has gained close attention and huge momentum in recent years. Several algorithms for analog VLSI layout automation are proposed hi this dissertation. The architecture and workflow of the tool is designed. Experimental results are given to demonstrate the validity and efficiency of the proposed algorithms. ha this dissertation, we designed the architecture and the workflow of the analog VLSI layout automation tool. The workflow includes input, stack generation, floorplan, routing and output. For stack generation, we proposed the concept of symmetrical Euler's graph and symmetrical Euler's trail, based on which algorithms for two dimension stack generation is proposed. The generated stacks are 2-axisle symmetric and common-centroid that minimum the mismatch. Algorithms for module merging are proposed, which are essentially independent to any topological representation. Module merging algorithms can exploit the possibility of area sharing during floorplanning, which reduce area occupation and minimum parasites. Since some modules need to be placed along the border of chip, algorithms based on O-tree for solving boundary constrains are proposed. Furthermore, for satisfying the needs of placing some modules along the common bus, algorithms for predefined coordinate align constrains are also presented. |
| Pages | 98 |
| Language | 中文 |
| Content Type | 学位论文 |
| URI | http://ir.iscas.ac.cn/handle/311060/6202 |
| Collection | 中科院软件所_中科院软件所 |
| Recommended Citation GB/T 7714 | 刘锐. 模拟集成电路版图设计自动化的研究[D]. 中国科学院软件研究所，清华大学计算机系. 中国科学院软件研究所，清华大学计算机系,2002. |
| Files in This Item: | ||||||
| File Name/Size | DocType | Version | Access | License | ||
| LW011202.pdf（2221KB） | 限制开放 | -- | Application Full Text | |||
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