| 其他摘要 | With the obviously increasing in system complexity and integration, the new phenomena appear, such as the increasing number of the components of high-speed communication equipment, the tightening density of PCB and the higher signal frequency and so on. In that case, the stability of the clock system, which is usually the most widely used system in electro circuit, is the most important premise and guarantee for the stability of high-speed digital systems. Therefore, the clock in high-speed circuit design is important. The integrality of signal and power in clock system is the most important guarantee to the logic of systematic clock, while EMC is also the necessity to take up the market.
Based on the clock system design of the Ethernet switch, the paper discusses the key technology in high-speed clock system design, including termination, hole, crosstalk, EMC, SNN, shunt capacitor and so on. Furthermore, combined with the hardware design of a network video server, it depicts the method of utilizing the technology in practice. Besides these, for deep research of clock system, the paper illustrates the way to exchange data from different clock domain based on the design of a high-speed asynchronous FIFO.
This paper consists of five chapters. The 1st chapter analyzes the background and the theme, including condition of the community broadband network system, the network video server and the network measurement system. In 2nd chapter, combined with clock system problem of the Ethernet switch SW1200, the character and the keystone of clock system are pointed out. Moreover, it introduces the method to do the board-level signal integrity simulation by Cadence. The 3rd chapter introduces the NVS and its detailed design. The 4th chapter states exchanging data from different clock domain based on the asynchronous FIFO. At last, the 5th chapter summarizes this paper and prospects the further work. |
修改评论